プラズマエッチング：市場分析および戦略的諸問題

Abstract

Future etch technology development, in support of future projected BEOL requirements, will include both dielectric and conductor classes of materials. Continual optimization of existing capacitively coupled based source technology is envisioned to adequately address the progression of shrinking line/space dimensions and associated via/contact diameters while overall aspect ratios maintain parity with current technology. Future memory technology development will require the introduction of progressively higher dielectric materials to partially offset cell area reductions. These materials as a class exhibit very low volatility by-products. The high aspect ratio contact etch is expected to be continually challenged based on ever increasing aspect ratios for each new technology node. It is anticipated that current inductively coupled source equipment will continue to address future needs.

Conductor etch requirements include the continuation of the stalwart Al etch, to at least the 90 nm technology node using existing inductively coupled plasma source technology. The introduction of progressively higher dielectric materials in support of future memory technology development are also anticipated to require new top and bottom metal electrode materials like noble and refractory metals. Currently, etch of these metal electrode materials are being addressed with existing capacitively coupled source equipment.

New interconnect and/or package technologies (e.g., 3D IC) are moving into manufacturing. One of the key technology challenges of this technology is the need to etch 100 micron vias from the interconnect layers, through the entire wafer providing for electrical (or sometimes thermal) connections on the back of the die. The use of Xenon containing gas mixtures will be critical.

Table of Contents

Chapter 1 Introduction

• 1.1 The Need For This Report

Chapter 2 Executive Summary

• 2.1 Summary of Technical Issues
• 2.2 Summary of User Issues
• 2.3 Summary of Supplier Issues
• 2.4 Summary of Market Forecasts

Chapter 3 Technical Issues and Trends

• 3.1 Introduction
• 3.2 Processing Issues
  • 3.2.1 Chlorine Versus Fluorine Processes
  • 3.2.2 Multilevel Structures
  • 3.2.3 New Materials
  • 3.2.4 GaAs Processing
• 3.3 Plasma Stripping
  • 3.3.1 Photoresist Stripping
  • 3.3.2 Low-K Removal
• 3.4 Safety Issues
  • 3.4.1 System Design Considerations
  • 3.4.2 Gas Handling
  • 3.4.3 Reactor Cleaning

Chapter 4 Market Forecast

• 4.1 Influence of Technology Trends on the Equipment Market
• 4.2 Market Forecast Assumptions
• 4.3 Market Forecast

Chapter 5 Strategic Issues: Users

• 5.1 Evaluating User Needs
  • 5.1.1 Device Architecture
  • 5.1.2 Wafer Starts and Throughput Requirements
  • 5.1.3 Wafer Size
• 5.2 Benchmarking a Vendor
  • 5.2.1 Pricing
  • 5.2.2 Vendor Commitment and Attitudes
  • 5.2.3 Vendor Capabilities
  • 5.2.4 System Capabilities
• 5.3 Cost Analysis
  • 5.3.1 Equipment Price
  • 5.3.2 Installation Costs
  • 5.3.3 Maintenance Costs
  • 5.3.4 Sustaining Costs
  • 5.3.5 Hidden Costs
• 5.4 User - Supplier Synergy
  • 5.4.1 Feedback During Equipment Evaluation
  • 5.4.2 Feedback During Device Production

Chapter 6 Strategic Issues: Suppliers

• 6.1 Competition
• 6.2 Customer Interaction
  • 6.2.1 Customer Support
  • 6.2.2 Cleanroom Needs in the Applications Lab
• 6.3 Equipment Compatibility in Class 1 Cleanrooms
  • 6.3.1 Footprint Versus Serviceability
  • 6.3.2 Particulate Generation
  • 6.3.3 Automation
  • 6.3.4 300-mm Tools

FIGURES

• 3.1 Various Enhanced Designs (a) Helicon, (b) Multiple ECR, (c) Helical Resonator
• 3.2 Schematic of Inductively Coupled Plasma Source
• 3.3 Schematic of the HRe Source
• 3.4 Schematic of the Dipole Magnet Source
• 3.5 Schematic of Chemical Downstream Etch
• 3.6 Silicon Trench Structure
• 3.7 Dual Damascene Dielectric Etch Approaches
• 4.1 Trends in Minimum Feature Size for Dynamic RAMS
• 4.2 Market Shares for Dry Etch Equipment
• 4.3 Market Shares for Strip Equipment
• 4.4 Distribution of Etch Sales by Type
• 4.5 Distribution of Etch Sales by Device
• 4.6 Geographical Distribution of Equipment Purchases
• 5.1 Typical First Year Single Wafer System Cost Analysis
• 6.1 Relationship Between Device Yield and Particles
• 6.2 Sources of Particles
• 6.3 Relationship Between Die Yield and Chip Size

TABLES

• 3.1 Silicon Wafer Usage
• 3.2 Plasma Source Comparison
• 3.3 Typical Process Specifications
• 3.4 Dry Resist Stripping Systems
• 4.1 Worldwide Dry Etch Market Shares
• 4.2 Worldwide Dry Strip Market Shares
• 4.3 Worldwide Market Forecast of Plasma Etching Systems
• 4.4 Distribution of Etch Sales by Device by Vendor
• 4.5 Number of Layers To Be Etched
• 4.6 Distribution of Wafer Starts
• 4.7 Feature Sizes of Equipment Capabilities
• 5.1 Levels of Integration of Dynamic Rams
• 5.2 Interconnect Levels of Logic Devices
• 6.1 0.18μm Etch Process Specifications